The invention described herein pertains to a polishing process for polishing semiconductor structures containing copper circuits utilizing polishing fluids with an abrasive content less than 3%.
One of the critical requirements for the production of increasingly complex and dense semiconductor structures is the ability to retain planarity of semiconductor substrates. Without the ability to planarize, the complexity and density of the structures constructed on a semiconductor wafer are greatly limited. Chemical-Mechanical Polishing, or CMP, is an enabling technology in this area, since it has proved to be the most effective method for planarization of surface films on semiconductor substrates.
While the first applications of CMP technology focused on the polishing of dielectric films (i.e., SiO2), polishing of metal structures used for circuit interconnects is increasing rapidly. Most metal structures contain three different films: a conductive metal layer (e.g., copper material), a barrier or liner (e.g. titanium or tantalum alloy) layer between the conductive metal layer and the adjacent dielectric layer, and a dielectric layer (e.g., silicon oxide). Integrated circuits are constructed by depositing layers of materials (metals, barrier layers and dielectric) on a wafer made of silicon oxide. After each layer is deposited, the layer is etched to create circuitry features. As a series of layers are sequentially deposited and etched, the outermost surface of the substrate, becomes increasingly non-planar. Nonplanar surfaces on the wafer result in defects in subsequent circuit layers leading to flawed circuitry. It is thus desirable to have planar surfaces.
Metal polishing slurries are designed to polish and planarize a conductive layer on a semiconductor wafer. The conductive layer is typically deposited on a dielectric layer and can be made of any conductive material such as tungsten, titanium, aluminum, copper, doped silicon, doped polysilicon, or a metal silicide layer. The dielectric layer typically has openings (xe2x80x9cviasxe2x80x9d) that are filled with the conductive material to provide a path through the dielectric layer to previously deposited layers. After polishing, the conductive material remains only in the vias in the dielectric layer. U.S. Pat. No. 5,340,370 describes a polishing process for metals and some slurries developed for metals polishing.
Additional detail about polishing pads may be found in U.S. Pat. No. 5,578,362 to Reinhardt et al.
U.S. Pat. No. 5,652,177 discusses polishing silicon at substrate holder pressures from about 250 to about 350 lbs per square inch and a platen rotational velocity of about 20 to about 60 rpm. U.S. Pat. No. 5,607,718 discusses increasing the ratio of polishing velocity of aluminum to dissolution velocity of aluminum with respect to the polishing agent to minimize dishing. U.S. Pat. No. 5,972,792 describes a method for chemical-mechanical planarization of a substrate on a fixed-abrasive polishing pad in which a planarizing solution is dispensed onto the fixed-abrasive polishing pad. WO 96/25270 describes abrasive-free polishing compositions containing hydrogen peroxide for polishing tungsten.
Wafer non-uniformity is a significant problem during CMP of semiconductor device wafers due to differences in removal rates (RR) between the center and edge of the wafer being polished. Typically, non-uniformity is expressed as within wafer non-uniformity (WIWNU or % NU). Typically, wafer non-uniformity is minimized by altering the various carrier head pressures on the wafer, such as, the retaining ring pressure, or utilizing different pad-conditioning processes.
The method of this invention maximizes global wafer uniformity during chemical-mechanical planarization of semiconductor devices with softer interconnect metals such as copper material. Additionally, a method for removal of copper material residuals during chemical-mechanical planarization of patterned semiconductor wafers is also presented.